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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
Table 44: REFRESH Command Scheduling Separation Requirements (Con-
tinued)
Minimum
Delay
Symbol
t RRD
From
REFpb
To
ACTIVATE command to a different bank than REFpb
Notes
ACTIVATE REFpb
ACTIVATE command to a different bank than the prior
ACTIVATE command
1
Note:
1. A bank must be in the idle state before it is refreshed, so REFab is prohibited following
an ACTIVATE command. REFpb is supported only if it affects a bank that is in the idle
state.
Mobile LPDDR2 devices provide significant flexibility in scheduling REFRESH com-
mands as long as the required boundary conditions are met (see Figure 57 (page 81)).
In the most straightforward implementations, a REFRESH command should be sched-
uled every t REFI. In this case, self refresh can be entered at any time.
Users may choose to deviate from this regular refresh pattern, for instance, to enable a
period in which no refresh is required. As an example, using a 1Gb LPDDR2 device, the
user can choose to issue a refresh burst of 4096 REFRESH commands at the maximum
supported rate (limited by t REFBW), followed by an extended period without issuing
any REFRESH commands, until the refresh window is complete. The maximum suppor-
ted time without REFRESH commands is calculated as follows: t REFW - (R/8) × t REFBW
= t REFW - R × 4 × t RFCab.
For example, a 1Gb device at T C ≤ 85?C can be operated without a refresh for up to 32ms
- 4096 × 4 × 130ns ≈ 30ms.
Both the regular and the burst/pause patterns can satisfy refresh requirements if they
are repeated in every 32ms window. It is critical to satisfy the refresh requirement in
every rolling refresh window during refresh pattern transitions. The supported transi-
tion from a burst pattern to a regular distributed pattern is shown in Figure 54
(page 78). If this transition occurs immediately after the burst refresh phase, all rolling
t REFW intervals will meet the minimum required number of REFRESH commands.
A nonsupported transition is shown in Figure 55 (page 79). In this example, the regu-
lar refresh pattern starts after the completion of the pause phase of the burst/pause re-
fresh pattern. For several rolling t REFW intervals, the minimum number of REFRESH
commands is not satisfied.
Understanding this pattern transition is extremely important, even when only one pat-
tern is employed. In self refresh mode, a regular distributed refresh pattern must be as-
sumed. Micron recommends entering self refresh mode immediately following the
burst phase of a burst/pause refresh pattern; upon exiting self refresh, begin with the
burst phase (see Figure 56 (page 80)).
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
76
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数
MT42L256M32D4KP-MS
制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk